My primary focus is analog and mixed-signal IC design, with work spanning transistor-level circuits, CMOS/VLSI, circuit simulation and physical verification.
I also develop electronic hardware and C/C++ software. That work ranges from Altium schematics and PCB layout to embedded systems, custom data structures and modular software architectures. Across these disciplines, my projects connect design decisions with simulation, implementation and testing.
A CMOS inverter developed from schematic and device sizing through physical layout, DRC/LVS and parasitic extraction. Spectre characterization and HSPICE post-layout simulation connect the physical design with its timing behavior.
Differential gain stages, a compensated two-stage op amp and a unity-gain-stable folded-cascode op amp. The designs bring together gm/Id sizing, bias allocation, frequency compensation and AC/transient verification.
Transistor-level inverter chains, a 256-wordline decoder, latches, registers and XOR datapaths. Logical effort and device sizing inform the design, with simulation used to verify combinational delay and sequential timing.
A functioning, battery-powered OPA1652 amplifier developed through Altium schematic capture and two-layer PCB layout, fabrication, hand assembly and bench testing. A custom Fusion 360 enclosure completes the physical design.
A modular historical-market analyzer and trading-strategy simulator, co-developed in C++. Custom data structures, explicit memory management and polymorphic strategies support portfolio operations, historical-data processing and backtesting.
A text-based game combining map generation, timed gameplay, collision handling and scoring. The project brings together input handling, changing game state and terminal rendering in C.
An AVR assembly system connecting analog acquisition, numerical conversion, asynchronous serial communication and an LCD. The implementation works directly with peripheral registers, timing and display updates.
An ongoing, three-person project integrating propulsion, power, flight control and live video. Current work addresses component selection and the relationships between mass, energy demand, endurance and system compatibility.
Technical evaluation of AI responses for correctness, completeness and instruction adherence, with written feedback identifying errors and actionable improvements.
My work spans low-voltage electrical architecture, component selection, sourcing and bench testing for Stony Brook’s inaugural Formula SAE team. Component decisions account for electrical requirements, redundancy, availability, lead time and cost.
I contribute to system planning for ECU and sensor integration, wiring harnesses, power distribution, protection, grounding and noise control. This includes component-market and cost data for the vehicle BOM, alongside concepts for brake- and fault-triggered shutdown behavior.
I worked with logistics and management teams, plant personnel and international technical staff across rebar and corrugated-steel operations. The work covered raw-material sourcing, machinery and furnace systems, energy use, waste handling and production flow.
Following the process from sourcing to distribution provided a view of how technical requirements, material quality, production demand and budget interact in large-scale manufacturing.
Analog amplifiers, transistor-level CMOS, device sizing and timing analysis. My Cadence work spans schematic design and Spectre simulation through physical layout, Calibre DRC/LVS and extraction, with HSPICE for post-layout verification. Analog design work also uses PSpice/OrCAD and LTspice.
Altium schematic capture and PCB layout through manufacturing outputs, component assembly and board bring-up. My hardware work includes oscilloscope and audio validation, with Fusion 360 for enclosure design. KiCad is also part of my PCB toolset.
Modular applications, custom data structures and explicit memory management. My C++ work includes linked lists, iterators, queues, stacks and binary search trees, using templates and polymorphism to separate reusable infrastructure from application logic. My C work includes a real-time text-based game.
Register-level AVR development, ADC acquisition, asynchronous USART communication and LCD interfacing. At system level, my work covers component selection and testing, power distribution, sensor integration and electrical-system planning.